1. Field of the Invention
The present invention generally relates to polling techniques used in data processing systems and, more particularly, to polling techniques that work in conjunction with existing cache coherent protocols to significantly improve overall system performance.
2. Description of the Prior Art
In environments where there is a level of parallelism between software and a hardware device, for proper flow of control there is a need for synchronization. A typical scenario is one where software passes a packet of data to a device and wants to know if the device has completed acting on the data. Usually the device exposes an abstraction of a status register for software to query state. A series of repeated queries is referred to as a polling loop. When the device finally completes the previously dispatched task, the reflected state in the status register is read by software, which causes it to exit the loop and proceed with its normal processing. While polling loops do not perform any useful work, they are sometimes unavoidable.
The biggest problem with this approach is that a substantial portion of the system resources are tied up while software stays in the polling loop. Usually, devices are quite far from the processor complex, attached to some input/output (I/O) bus. In order to query status, the processor executes a series of load, compare, branch instructions. The load instruction sees the latency of the system buses and the device itself. A tight polling loop generates these load instructions at a very rapid pace, which in turn saturates the available system bus bandwidth. This implies that another critical activity on the machine that is dependent on the system bus is insufficiently serviced. In many situations, the device itself may be relying on use of the system bus in order to complete its task. Hence, the act of polling across the bus actually comes in the way of device response.